High Performance Data Encryption based on Advanced Encryption Standard using FPGA

Many digital services, such as confidential video conferencing, medical, military imaging systems and the rapid progress of Internet, require reliable security and encryption in real time to store and transmit these digital images/videos.In this paper, a parallel implementation of the advanced encryption standard (AES) using pipelining technique is proposed. For more security, a pseudo random sequence generator (PRSG) is used in advance. The goal is to achieve a high-speed reliable security system for real time application. The parallel architecture is implemented on Field Programmable Gate Arrays (FPGA) family of Spartan_6 (XC6SLX16) using Very high speed Hardware Description Language (VHDL). An image encryption is taken as a case study. The system is capable to process image (256*256) in (0.00053) seconds; consequentially the real time requirement is achieved.